The present invention relates to an A/D converter circuit capable of compensating A/D-converted values.
A conventional A/D converter circuit is disclosed in Japanese Laid-open Patent Publication No. 7-27364. The conventional A/D converter circuit is designed to cancel an off-set voltage generated by the conventional A/ID converter circuit. This conventional A/D converter circuit will be described with reference to FIG. 1. The conventional A/D converter circuit comprises an A/D converter 1 for converting analog input signals 11 into digital output signals 12, an off-set compensating register 8 for receiving the digital output signals 12 from the A/D converter 1 to output an off-set compensating code 25 in accordance with a control signal 24, and a subtracter 2 for receiving both the digital output signals 12 from the A/D converter 1 and the off-set compensating code 25 from the off-set compensating register 8 so as to compensate the digital output signals 12 with the off-set compensating code 25, thereby outputting digital output signals 26 with compensated off-set voltages.
For starting operations of the above A/D converter circuit, an offset compensating code for the off-established compensating register 8 is set in the A/D converter 1. The analog input signal 11 corresponding to "0" level is inputted into the A/D converter 1. In response to the input of the analog input signal 11 corresponding to "0" level, a digital output signal 12 is outputted from the A/D converter 1 and then transmitted into the off-set compensating register 8, before the digital output signal 12 is held in the off-set compensating register 8. The digital output signal 12 output in response to the input of the analog input signal 11 corresponding to "0" level is just a digital value corresponding to the off-set voltage generated by the A/I) converter 1, for which reason this digital value corresponding to the off-set voltage is held in the off-set compensating register 8 as an off-set compensating code for compensating the off-set voltage generated by the A/D converter 1. In the initial state of the A/D conversion operations, the off-set compensating code for compensating the off-set voltage generated by the A/D converter 1 is set in the off-set compensating register 8 for subsequent fetching the off-set compensating code before substantive A/D conversion.
Subsequently, the substantive A/D conversion will be made as follows. The digital output signal 12 output in response to the input of the analog input signal, 11 is then inputted into the subtracter 2 being under the control of the control signal 24, whilst the subtracter 2 is operated to fetch the off-set compensating code 25 from the off-set compensating register 8 for subsequent subtraction of the off-set compensating code 25 from the digital output signal 12, whereby the digital output signal 26 is obtained by subtracting the off-set compensating code 25 from the digital output signal 12 before the digital output signal 26 is then outputted from the subtracter 2.
The above conventional A/D converter circuit has the following disadvantages. As described above, the above conventional A/D converter circuit executes the subtraction operation only with the off-set compensating code corresponding to the off-set voltage generated by the A/D converter, for which reason the above conventional A/D converter is capable of compensation to the off-set voltage of the A/D-converted digital signal outputted from the A/D converter 1. Notwithstanding, the above conventional A/D converter is incapable of compensations to integral linearity error and to gain error in the A/D converter 1.
In the above circumstances, it had been required to develop a novel A/D converter circuit capable of not only compensating the off-set voltage of the A/D-converted digital signal outputted from the A/D converter but also compensating both integral linearity error and gain error in the A/D converter.